The present invention relates to a high definition television (HDTV) receiver, and more particularly, to a HDTV receiver which is improved in its overall performance and is simplified in its configuration, by improving a symbol timing restoring circuit.
FIG. 1 is a block diagram of a conventional 8-vestigial sideband (VSB) receiver, in which a high-frequency signal input from an antenna (ANT) is demodulated and is carrier-restored when a channel is a selected in a tuner 1 and a signal having a central frequency of 44 MHz is automatic-gain controlled and IF-bandpass filtered in an IF processor & carrier restoring portion 2.
This signal is digitally sampled in an analog-to-digital conventer (ADC) 3 and precise symbol timing is detected by a timing restoring portion 4, thereby controlling the timing of ADC 3.
The output of ADC 3 is also input to a sync detector 5 to detect a data segment sync from a data segment sync pattern (FIG. 3A) and to detect a field sync from a field sync pattern being in the first line of a transmission format.
At this time, the data segment sync and field sync detected in sync detector 5 are used as the control signals of subsequent blocks 7 through 16.
NTSC (National Television System Committee) interference detector 7 receives a signal passing through a post-comb filter 6 and a signal not passing therethrough and determines whether there is an identical channel interference with that of NTSC or not, to then transmit a comb control signal SC1.
If there is no NTSC identical channel interference, the signal not passing through post-comb filter 6 is selected by a multiplexer 8. A channel equalizer 9 equalizes the incoming signal which is set to 8 levels to remove the intersymbol interference due to a ghost generated at the channel.
Also, a phase corrector 10 corrects the phase error remaining after signal-processing, setting the incoming signal to 8 levels. An optimal viterbi decoder 11 performs a 4-state viterbi decoding operation and the decoded output is output through multiplexer 13.
If there is NTSC identical channel interference, the output of post-comb filter 6 is selected as the output of multiplexer 8. At this time, post-comb filter 6 subtracts data delayed for 12 symbol period from the current data.
Therefore, the original 8 level data becomes 15 level data. The NTSC identical channel interference is removed. At this time, channel equalizer 9 and phase controller 10 operate assuming that the incoming signal is 15 level data, and multiplexer 13 selects and outputs the output of a partial response (PR) viterbi decoder 12.
PR viterbi decoder 12, an 8-state decoder, has much more complex structure than that of optimal viterbi decoder 11.
The output of multiplexer 13 is dissipated in order to enhance the correction capability for burst errors in a deinterleaver 14. An error controller 15 performs a Reed-Solomon decoding operation.
Also, a derandomizer 16 releases a signal randomly formed in a transmission port reversely. Timing restoring portion 4 is constituted by a data segment sync detector 4a and a phase locked loop (PLL) 4b, as shown in FIG. 2. The digitally converted signal is concurrently output to data segment sync detector 4a and PLL 4b.
At this time, data segment sync detector 4a detects a data segment sync, based on the data pattern "1001" for 4 symbol period of 2 levels shown in FIG. 3A.
PLL 4b detects the phase error for the timing from a data segment sync pattern. The output of a phase detector is as shown as FIG. 3B, digitally, and as FIG. 3C, analogically.
The position of a sampling point 4 shown in FIG. 3C is a zero-crossing point, and a symbol timing is detected using the zero-crossing point.
However, the aforementioned conventional art adopting a post-comb filter for reducing the NTSC identical channel interference has a very complex configuration.